In Verilog HDL, the difference between `always @(*)` and `always @(posedge clk)` blocks is which?
ABoth are equivalent to wire assignments at all times only
BBoth blocks infer flip-flops always under any case
CBoth blocks infer pure combinational always under any
DCombinational vs sequential (clocked)
Answer & Solution
Correct answer: D. Combinational vs sequential (clocked)
`always @(*)`: sensitivity to all RHS inputs, synthesises combinational logic. `always @(posedge clk)`: edge-triggered, synthesises flip-flops/registers (Wakerly Ch.5).
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